What does process size mean?
90 nm. 65 nm. 45 nm. If you follow computer processors, chipsets, or video cards very closely at all, you have likely heard at least a passing reference to "process size". But without any explanation, it's hard to even guess at what this phrase means. Luckily, we can change that. We can not only delve into the physical meaning of process size, but also its impact on power consumption and cost.
All semiconductor devices are manufactured as a series of layers on some substrate material (normally silicon dioxide). The exact specifics can vary considerably, but at a high level of abstraction you can think of a semiconductor as a series of very thin, stacked layers. Each layer is created from a different mask, and different layers can be made of different materials. Transistors are normally created by stacking the poly and active layers in a particular way. Capacitors can be created by stacking two different metal layers, or a variety of other ways.
The masks used to create each layer are basically like a 1-bit bitmap: they have a grid of squares (similar to pixels) that are either "on" or "off". And this is where process size comes into play. The process size defines lambda, which is how large each of those squares will be on the chip.
The properties of semiconductor devices, like other electronic devices, are based on the relative sizes of their dimensions. So a resistor, for instance, that is made of a 4 lambda x 20 lambda rectangle will have essentially the same resistance for any value of lambda. Similarly (and this is key for computer chips), if you take all the components of a transistor and double or halve all of their dimensions, you will end up with a transistor that performs quite similarly either way.
So in the semiconductor world, all dimensions are sized in units of lambda. A standard via (which, just like a via on a circuit board, is used to connect different layers) is 2 lambda x 2 lambda, for instance.
There is a major stipulation there, though. If you reduce the value of lambda, your devices will behave very similarly, but not exactly the same. This is both good and bad.
As a high-level abstraction, you can pretend that each layer has zero thickness, including the insulative layers in between the layers that you use to draw your circuit. However, reality is not so kind. Layers have non-zero thickness, and their thickness doesn't scale to perfectly match when you change your value of lambda.
This means that if you move to a smaller value of lambda (a smaller process node), interesting things can happen. For instance, suppose you have a capacitor made up of two stacked squares of metal. The capacitance (analogous to resistance) of that capacitor is directly proportional to the area of the plates, and inversely proportional to the distance between them (and also directly proportional to a material proprty that we will treat as constant for simplicity).
If you divide lambda in half, you divide the area of the plates by four (no magic, just geometry). Unless you also divide the thickness of the layer(s) between the plates by four, you will end up with a capacitor with lower capacitance.
If you are in the business of making capacitors, that is inconvenient. On the other hand, if you are in the business of making chips with millions of transistors (as Intel, AMD, NVIDIA, et al, are), this is great. Real-world transistors have capacitance between their terminals, which gets in the way of increasing the switching frequency of those transistors. And even more important, the dynamic power a transistor consumes (the power it consumes when switching) is proportional to capacitance. So smaller transistors scale more easily to higher frequencies, and use less power.
But wait, there's more! Smaller transistors have lower "turn on" voltages, which means they can be driven by lower voltages (what are called core voltages). And dynamic power loss in a transistor is proportional to the square of that voltage; cut the voltage in half, cut power consumption by a factor of four.
All is not sunshine and roses, though. Smaller transistors have higher leakage currents, and they can create new headaches.
Leakage current is often compared to a leaking faucet: no matter how hard you try to close the valve, it is never quite completely closed. So it leaks a little bit. All else being equal, smaller transistors have to contend with higher leakage currents. There are all sorts of tweaks that can be done to the materials to combat this, but those can only do so much.
Leakage current translates into static power consumption, the power that a chip consumes even when it is sitting and doing nothing.
We have already pointed out a few times where the ideal assumptions we would like to use can break down. And here is another one: our chip is not the perfect grid of "on" and "off" squares that we would like it to be. There are a number of effects (random fluctuations, gradients, diffusion effects, etc.) that create more trouble as devices get smaller. A full discussion of these issues is beyond the scope of this particular article; suffice it to say that they all point to the non-ideal, analog reality of chip fabrication.
Sometimes to deal with these issues, we must make devices larger than we otherwise would. So perhaps we reduce lambda by half, but then have to scale some components up by a factor of 1.5 to deal with these other issues. So those components are now only 3/4 their original size, rather than 1/2.
This gets at one of the key reasons that manufacturers choose to switch to smaller processes: cost. The smaller a chip is, the cheaper it is to make.
Semiconductors are fabricated on wafers. Each wafer can contain dozens of individual dies (the actual semiconductor device that goes into a chip). The smaller each die is, the more dies (some people prefer the term dice) you can fit on each wafer.
Smaller process sizes demand an investment in more expensive equipment; but after that initial cost, the per-wafer cost difference is not huge. So by cramming more dies on each wafer, you can significantly decrease the cost to manufacture your product.
This is where Moore's law comes from. Moore's law states that roughly every two years, you can pack twice as many transistors into a chip at about the same cost. Historically, the industry has managed a transition to a smaller process node (such as the transitions from 130 nm to 90 nm to 65 nm) about once every two years. And each time, you can fit about twice as many transistors into the same physical area.
Process size governs the physical size of the components that make up a chip. Smaller process nodes can translate into reduced costs and lower power consumption. There are tradeoffs in difficulty and possibly power or cost, though (as they say, there's no such thing as a free lunch).
Did you ever wonder why the various process nodes use the particular values of lambda that they do? This is actually governed by a sort of "gentleman's agreement" between the numerous parties in the semiconductor industry. Years ago, they drew up the International Technology Roadmap for Semiconductors, a 15-year (!) roadmap for the industry. It specifies when node transitions should occur, as well as many of the details of the nodes. And amazingly, they have stayed quite close to it through the years.
OK, but why these exact numerical values of lambda? If you look at some recent nodes, you will see a logical progression. 130 nm, 65 nm, and soon 32 nm (divide by two). And staggered with these you will see 180 nm, 90 nm, and 45 nm (again, divide by two). The second set is roughly halfway between the first.
Those are the nodes that computer processors (that is, CPUs) have used. But there are other standard nodes that they have skipped. The foundries have made use of some of these other nodes, as have the graphics processing units (GPUs) that go into graphics cards. That's not a coincidence; unlike CPUs, GPUs are currently all designed by a fab-less company and then fabricated by a foundry. In any case, these process nodes (such as 110 nm, 78 nm, and 55 nm) are sometimes refered to as "half nodes" because they sit halfway between the other nodes.
All of the nodes we have listed (and indeed, any node with a lambda smaller than 250 nm), are known as "deep sub-micron" nodes. In other words, they have a lambda that is significantly smaller than 1 micron (1 um, or 1000 nm). Slightly larger (but still smaller than 1 micron) nodes are refered to as "sub-micron" nodes.
If you pay any attention to analog products, you may notice that they tend to trail well behind digital devices in
We have tried very hard to avoid too much jargon in this article, although some jargon is necessary just to provide a decent explanation of the topic. To clear up any confusion over any jargon used above, and also to help with any jargon you might see elsewhere, we have included a brief glossary below.
- Complementary MOS. A device made of both n-type and p-type MOSFETs.
- Die shrink
- Taking an existing design and shrinking it down for use with a new, smaller lambda, without making major design changes
- The insulating layer between the plates of a capacitor, or between the gate and source/drain of a transistor.
- Feature size
- The physical size of the features that can be created in a design, often used as a rough synonym for process node.
- The nominal "input" of a MOSFET, one of its three terminals.
- High-k dielectric
- A dielectric material with a high dielectric constant. This allows for a thicker dielectric layer without a dramatic change in capacitance, and a thicker dielectric layer reduces leakage current.
- The "metric unit" that all parts are specified in proportion to. Normally the lowercase version of the (Greek) character is used: λ.
- Also known as photolithography, this is the actual process used to create each layer of a chip. Normally, some material is deposited on the substrate, and then coated in a photoresist material. This is then exposed to UV light, an etchant is applied, and the remaining photoresist is cleaned away.
- A screen that selectively lets light through or blocks it, used in lithography.
- Metal-Oxide-Semiconductor Field Effect Transistor, a transistor with a metal gate, oxidized insulator, and semiconductor source and drain, that operates by way of a field effect. In practice, the gate is often note actually metal, but polysilicon.
- Polysilicon, the layer normally used to construct the gate of a transistor (except in metal-gate transistors, which use a metal layer).
- Process node
- The combination of a particular value of lambda and a set of design rules, meant to ensure that a design can be compatible with equipment from different manufacturers or facilities.
- A "vertical" metal interconnect, used to connect different layers to each other.
For further reading, Ars Technica has an overview of the significance of changing process size. If you'd like to delve into the topic of chip fabrication in general, you might start with the "virtual factory tour" provided by NEC.